Ramp generator with fast reset
US7388413B1 · kind B1 · utility
9Cited by
32References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 14, 2005 |
| Grant date | Jun 17, 2008 |
| Priority date | — |
| Expiry date | Jul 31, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K4/501
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An efficient ramp generator uses a reversing switch array to couple a timing capacitor in alternating polarities between an input terminal and an output terminal of an operational amplifier to generate a periodic ramp signal without discharging the timing capacitor between voltage ramps. The reversing switch array includes at least four semiconductor switches controlled by a flip-flop circuit or a latch circuit. The flip-flop circuit or the latch circuit can be driven by an external clock signal or an internal clock signal with a variable frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.