Circuit and method to speed up PLL lock-time and prohibit frequency runaway
US7388440B1 · kind B1 · utility
5Cited by
25References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2004 |
| Grant date | Jun 17, 2008 |
| Priority date | — |
| Expiry date | Dec 2, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A lock-aid circuit and method is applied to a phase lock loop (PLL) having a voltage controlled oscillator (VCO), wherein the lock aid is coupled with the input of the VCO. In one example, the lock aid includes a Schmitt trigger having an output, a switch having an output and an input coupled to the output of the Schmitt trigger, and a voltage controlled current source coupled with the output of the switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.