Method for an element using two resist layers
US7388542B2 · kind B2 · utility
2Cited by
23References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2005 |
| Grant date | Jun 17, 2008 |
| Priority date | — |
| Expiry date | Mar 17, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49016
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A two resist layer process allows a seed layer to be used to electroplate a conductive layer of an element in a way that a portion of the seed layer can be removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.