Memory protected against attacks by error injection in memory cells selection signals
US7388802B2 · kind B2 · utility
2Cited by
8References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2006 |
| Grant date | Jun 17, 2008 |
| Priority date | — |
| Expiry date | Sep 15, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.