Method to reduce soft error rate in semiconductor memory
US7389446B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 16, 2004 |
| Grant date | Jun 17, 2008 |
| Priority date | — |
| Expiry date | Jul 21, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing soft error rates in semiconductor memory. In one embodiment, memory is partitioned into a) boot and download memory, b) program memory and c) data memory. Each partition receives protection according to the importance of the data stored. The boot memory is protected by sensing errors and repairing them utilizing on-chip data storage redundancy and exchange. The program memory is protected by sensing errors and repairing damaged data by reloading it using the program stored in the boot and download memory. The data memory is selectively protected similar to the program memory, but with the added feature of regular saving to disk from which to check for accurate data in the event of corruption. In another embodiment, any or all of the soft error protection features are selectable on a global basis, a memory type basis or, in the cases of program and data memory, on a block level basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.