Apparatus for providing capacitive decoupling between on-die power and ground conductors
US7391110B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2005 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Aug 10, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/924
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides capacitive decoupling on the surface of a semiconductor die, instead of providing the decoupling on a package or printed circuit board to which the semiconductor die is attached. In this embodiment, a surface of a semiconductor die includes exposed power and ground conductors, which are electrically coupled to internal power and ground nodes within the semiconductor die. To provide the wafer-level decoupling, a plurality of bypass capacitors are electrically coupled between pairs of exposed power and ground conductors, so that the plurality of bypass capacitors reduce voltage noise between the power and ground conductors on the semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.