Comparison circuit for analog/digital converter
US7391352B2 · kind B2 · utility
0Cited by
2References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 13, 2004 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Nov 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/365
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention pertains to a comparison circuit for an analog/digital converter. In order to reduce the effect of the offset voltages of the various comparators of the comparison circuit, voltage followers and a resistor network delivering at its outputs, mean voltages that are the average of those present on outputs of the comparators are linked downstream of the outputs of the comparators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.