Semiconductor memory device and arrangement method thereof
US7391636B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2007 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Sep 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device and an arrangement method thereof are included. The semiconductor memory device includes column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.