Microengine to network processing engine interworking for network processors
US7391776B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2003 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Mar 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/324
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus to control interaction between two multi-threaded processor engines is presented. A first multi-threaded processor engine is configured for connection to a serial link, and performs receive and transmit operations in a first “PHY” mode of operation. A second multi-threaded processor engine is operable to process data received by the first multi-threaded processor over the serial link and to provide the processed data to the first multi-threaded processor engine for transmission over the serial link, when the first multi-threaded processor operates in the PHY mode. Additionally, the first multi-threaded processor engine is configured to execute certain operations, e.g., hardware accelerator operations, at the request of the second multi-threaded processor engine in a second “co-processor” mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.