Memory access bandwidth allocation and latency control in a digital camera
US7392330B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 2004 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Oct 2, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S358/906
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory access bandwidth within a digital camera is allocated among several requestors by assigning each requester a “tokens per snapshot” (TPS) value. Each requestor has a DMA engine and a DMA entry queue. If the requester wishes to access the memory, then a DMA entry is pushed onto the DMA entry queue of the requester. An arbiter uses the TPS values to select DMA entries off the various queues for incorporation into a “snapshot”. The arbiter then selects DMA entries from the snapshot in an order for servicing such that memory access overhead in accessing the memory is reduced. Only after all DMA entries of the snapshot have been serviced is another snapshot of entries selected. Maximum latency in servicing a queue is controlled by assigning each queue a time out value (TOV). If a queue times out, then that queue is moved up in the order of servicing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.