Systems and methods for buffering data between a coherency cache controller and memory
US7392347B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 10, 2003 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Dec 30, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1668
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention is directed to a system processing memory transaction requests. The system includes a controller for storing and retrieving cache lines and a buffer communicatively coupled to the controller and at least one bus. The controller formats cache lines into a plurality of portions, implements an error correction code (ECC) scheme to correct a single-byte error in an ECC code word for pairs of the plurality of portions, stores respective pairs of plurality of portions such that each single-byte of the respective pairs of the plurality of portions is stored in a single one of a plurality of memory components. When the controller processes a memory transaction request that modifies tag data without modifying cache line data, the buffer calculates new ECC data utilizing previous ECC data, previous tag data, and the new tag data without requiring communication of cache line data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.