Microprocessor apparatus and method for optimizing block cipher cryptographic functions
US7392400B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2004 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | May 17, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides an apparatus and method for performing cryptographic operations on a plurality of input data blocks within a processor. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a cryptographic instruction and translation logic. The cryptographic instruction is received by fetch logic in a microprocessor as part of an instruction flow. The cryptographic instruction prescribes one of the cryptographic operations. The translation logic translates the cryptographic instruction into micro instructions. The micro instructions are ordered to direct the microprocessor to load a second input text block and to execute the one of the cryptographic operations on the second input text block prior to directing the microprocessor to store an output text block corresponding to a first input text block. Consequently, the output text block is stored during execution of the one of the cryptographic operations on the second input text block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.