Enhancing data integrity and security in a processor-based system
US7392404B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Mar 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A smart card which includes a non-volatile read/write memory and a processor connected to the memory, and further configured to cause the processor to perform a method for enhancing data security and managing the contents of memory during periods when the computational power of the processor is underutilized. The method includes steps for determining if a command or character has been received, processing and/or responding to the command or character once received, implementing a security measure and/or managing memory, and performing a tamper protocol in response to detecting a security breach, all of which is performed while waiting to receive the next command or character.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.