Universal parity encoder
US7392464B1 · kind B1 · utility
8Cited by
4References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2004 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Nov 2, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data encoding system for a data stream comprises an interleaving module that receives the data stream as N bit data blocks and that reverses positions of at least two of the N bits of selected ones of the data blocks. A generating module generates P error checking bits for each of the N bit data blocks. An insertion module receives the P error checking bits from the generating module and inserts the P error checking bits into the corresponding data block received from the interleaving module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.