Delamination reduction between vias and conductive pads
US7394159B2 · kind B2 · utility
6Cited by
6References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2005 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | Nov 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/0989
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Vias and conductive pads configured and coupled in a manner to reduce delamination are described herein. The via and the conductive pads may be located in a substrate such as a carrier substrate, a die, or a printed circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.