High voltage tolerant output buffer
US7394291B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2006 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | Dec 22, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high voltage tolerant output buffer uses a substrate voltage control circuit to control the voltage at the substrate of the transistors in the output buffer. The circuitry of output buffer is such that the voltage between any two terminals of any of the transistors is not allowed to exceed the supply voltage of the output buffer. At the same time, the voltage at the source or drain of transistors of output buffer is not allowed to increase beyond its substrate voltage. The proposed circuit for output buffer can tolerate voltages higher than the voltage at which it is operated. The novel circuitry uses less hardware and prevents power dissipation in the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.