Semiconductor memory device which prevents destruction of data
US7394691B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2006 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | Sep 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of memory cells each storing n values (n is a natural number which is not smaller than 3) are arranged in a matrix form in a memory cell array, and each memory cell is connected with a word line and a bit line. Each memory cell stores the n-valued data by a first write operation and a second write operation. A read section sets a potential of a word line, and reads data from a memory cell in the memory cell array. If data read by the read section and written in the second write operation includes an uncorrectable error, a control section changes a potential of a word line supplied to the read section when reading data written in the first write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.