Circuit implementation of a dynamic power supply for SRAM core array
US7394714B2 · kind B2 · utility
7Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2006 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | Oct 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SRAM device includes at least one memory cell having a source line for receiving an internal supply power, and a voltage management circuit coupled to the source line for generating the internal supply power that varies in at least two different voltage levels, depending on various operation modes of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.