Method and apparatus for performing horizontal addition and subtraction
US7395302B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2003 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | May 20, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs operations on data elements in the first packed data to generate a plurality of data elements in a second packed data in response to receiving an instruction. At least two of the plurality of data elements in the second packed data store the results of an intra-add operation, at least one of these results coming from the operation on data elements of the first packed data. One embodiment of a software method utilizes horizontal intra-add instructions for performing butterfly computations as may be employed, for example, in Walsh-Hadamard transforms or in Fast-Fourier Transforms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.