Macroscalar processor architecture
US7395419B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 23, 2004 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | Oct 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A macroscalar processor architecture is described herein. In one embodiment, an exemplary processor includes one or more execution units to execute instructions and one or more iteration units coupled to the execution units. The one or more iteration units receive one or more primary instructions of a program loop that comprise a machine executable program. For each of the primary instructions received, at least one of the iteration units generates multiple secondary instructions that correspond to multiple loop iterations of the task of the respective primary instruction when executed by the one or more execution units. Other methods and apparatuses are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.