Integrated circuit with integrated debugging mechanism for standard interface
US7395454B1 · kind B1 · utility
5Cited by
17References
44Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2005 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | Jun 19, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/273
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit having a corresponding method comprises one or more circuits each to produce one or more status signals, wherein each of the status signals represents a status of a respective one of the one or more circuits; a memory; a memory controller to store a plurality of samples of the one or more status signals in the memory; a plurality of input/output terminals; an interface in communication with one or more of the input/output terminals; and a debug circuit to transfer the one or more samples of the status signals from the memory to the interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.