Method and apparatus for performing error-detection and error-correction
US7395483B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2004 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | Jul 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2906
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that facilitates detecting and correcting errors. The system operates by receiving a data packet comprised of p words on a communication pathway, wherein each bit of a word is received on a separate data line in a set of data lines that comprise the communication pathway. The system also receives a time signature t on the communication pathway, wherein t contains per-bit error information for the p words in the data packet. As the data packet is received, the system performs an error-detection operation on each data bit of the data packet in parallel, wherein the error-detection operation generates per-bit error information for each bit position across the p words in the data packet. Finally, the system compares the generated per-bit error-information with the corresponding per-bit error information in the time signature t to determine if there exists an error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.