Control system and memory control method executing a detection of an error in a formation in parallel with reading operation
US7395489B2 · kind B2 · utility
6Cited by
9References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2003 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | Jul 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory control device includes a writing unit writing information to a memory module, a reading unit reading the information from the memory module, an error detecting unit executing a detection of an error in the formation in parallel with the reading operation by the reading unit, an error correcting unit correcting the error in the information containing the error detected, and a control unit controlling a transfer and a receipt of the information to and from an external device and stopping, when the error is detected, an output of the information to the external device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.