LDPC decoding methods and apparatus
US7395490B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2004 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | May 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0045
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.