Data aligner in reconfigurable computing environment
US7395517B2 · kind B2 · utility
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11References
7Claims
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Key dates
| Filing date | Sep 20, 2005 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | Jun 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/45
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.