Apparatus to passivate inductively or capacitively coupled surface currents under capacitor structures
US7397105B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | Oct 12, 2005 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Apr 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A deep n-well is formed beneath the area of a capacitor structure. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively and/or capacitively coupled surface currents to small areas that are then isolated from the rest of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.