Highly parallel switching systems utilizing error correction
US7397799B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2004 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Jun 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/557
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An interconnect structure comprises a logic capable of error detection and/or error correction. A logic formats a data stream into a plurality of fixed-size segments. The individual segments include a header containing at least a set presence bit and a target address, a payload containing at least segment data and a copy of the target address, and a parity bit designating parity of the payload, the logic arranging the segment plurality into a multiple-dimensional matrix. A logic analyzes segment data in a plurality of dimensions following passage of the data through a plurality of switches including analysis to detect segment error, column error, and payload error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.