Image processing device and image processing method
US7397951B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2004 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Feb 9, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
SRAMs A, B, C, and D having pixel data of each small block of each large block, for example a small block Aij for the SRAM A, to simultaneously read out a plurality of pixel data in the small block by specifying an address assigned to each small block, and a matrix of coefficient in which a matrix of plural coefficients are arranged are provided. Also provided are a coefficient matrix controller 12 and an adding section 13 to multiply the plural coefficients respectively by pixel data corresponding to each thereof and obtain a sum of the multiplied results. Each pixel data of each small block forming one large block, the pixel data being read out from the SRAMs A, B, C, and D, are multiplied by the coefficient matrix rearranged into a predetermined order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.