Method and system for DMA optimization in host bus adapters
US7398335B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2004 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Dec 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and system for optimizing DMA request processing is provided. The system includes a HBA that uses a dynamic DMA maximum write burst count sizing to optimize processing of write and read requests, wherein the HBA includes a DMA optimizer module that selects a certain write burst size to adjust performance when read and write DMA requests are being utilized. The DMA optimizer module can toggle between write and read request priority based on a maximum write request burst size. A shorter maximum write burst size provides more opportunity to issue read requests and a larger maximum burst size provides a better write request performance. The method includes, evaluating a read request throughput rate; evaluating a write request throughput rate; evaluating a read request utilization rate; evaluating a write request utilization rate; and adjusting a maximum write burst size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.