Methods and apparatus for dynamic instruction controlled reconfigurable register file
US7398347B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2004 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Sep 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For example, with separate files of the size 32×32 supported configurations of 128×32 bit s, 64×64 bit s and 32×128 bit s can be in operation each cycle. Single width, double width, quad width operands are optimally supported without increasing the register file size and without increasing the number of register file read or write ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.