Atomic operation involving processors with different memory transfer operation sizes
US7398368B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2005 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Sep 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/521
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Atomic operations may be implemented on a processor system having a main memory and two or more processors including a power processor element (PPE) and a synergistic processor element (SPE) that operate on different sized register lines. A main memory address containing a primitive is divided into a parity byte and two or more portions, wherein the parity byte includes at least one bit. A value of the parity byte determines which of the two or more portions is a valid portion and which of them is an invalid portion. The primitive is of a memory size that is larger than a maximum size for atomic operation with the PPE and less than or equal to a maximum size for atomic operation with the SPE. Read with reservation and conditional write instructions are used by both the PPE and SPE to access or update a value of the atomic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.