Method and apparatus for a low-density parity-check decoder
US7398453B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 3, 2005 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Jan 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/255
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low-density parity-check (LDPC) decoder (304) has a memory (308), and a processor (306). The processor is programmed to initialize (202) the LDPC decoder, calculate (204) a probability for each check node, calculate (206) a probability for each bit node, calculate soft decisions, update the bit nodes according to the calculated soft decisions, calculate (208) values from the calculated soft decisions, perform (210) a parity check on the calculated values, update (218) log-likelihood ratios (LLRs) if a bit error is detected in the calculated values, update the bit nodes according to the updated LLRs, and repeat the foregoing post initialization steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.