Method and apparatus for implementing decode operations in a data processor
US7398458B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 8, 2006 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | May 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6505
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved method and apparatus for performing operations (such as Viterbi decode) in digital processors using a reduced number of cycles. In one aspect, the invention comprises efficient methods for performing multiple “butterfly” add-compare-select (ACS) operations using an improved dual butterfly (DVBF) extension instruction added to the instruction set of a user-configured processor. The DVBF extension allows performance of two butterfly operations in a single cycle. In another aspect, an improved path metric addressing scheme is disclosed. An integrated circuit (IC) device incorporating the aforementioned features, and method of designing such IC, are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.