Isolated pwell tank verification using node breakers
US7398493B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2006 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Dec 16, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for checking a layout design of an integrated circuit is disclosed. The technique has application to converting the design of a circuit from schematic to layout form. Instances where multiple pwell isolation tanks are coupled to the same node and where one or more pwell isolation tanks are shorted to a substrate are detected. Node breakers are inserted in the layout between pwell isolation tanks coupled to the same node and between the substrate and isolated pwell tanks coupled to the substrate. The node breakers are inserted in the circuit schematic as well to satisfy a layout versus schematic comparison. Inserting the node breakers highlights circuit component groupings as well as which tanks contain certain elements, if any. This allows designers to make a conscious decision as to the location and groupings of elements in a layout design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.