Method for manufacturing semiconductor package substrate
US7399399B2 · kind B2 · utility
12Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2006 |
| Grant date | Jul 15, 2008 |
| Priority date | — |
| Expiry date | Mar 31, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49156
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor package is proposed. A circuit board with a circuit layer on at least one surface thereof is provided. The circuit board has at least one free area, and the circuit layer has a plurality of electrically connecting pads distributed on the periphery of the free area. A metal protecting layer is plated on the electrically connecting pads by non-plating line. The free area is removed, to form a cavity penetrating the circuit board. The present invention prevents burrs which may otherwise form on the periphery of a cavity, to increase the yield and throughput.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.