Digital power-on reset
US7400179B2 · kind B2 · utility
8Cited by
7References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 29, 2006 |
| Grant date | Jul 15, 2008 |
| Priority date | — |
| Expiry date | Jan 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00247
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a plurality of flip-flops and a compare circuit. The flip-flops may each be configured to (i) receive a clock signal and an input signal and (ii) generate an output signal. The flip-flops may be configured in series such that the output signal of a first of the flip-flops is presented as the input signal to a second of the flip-flops. The compare circuit may be configured to generate a reset signal in response to each of the output signals. The reset signal is generated until each of the output signals matches a set of predetermined values stored in the compare circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.