Complex-shaped video overlay using multi-bit row and column index registers
US7400328B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2005 |
| Grant date | Jul 15, 2008 |
| Priority date | — |
| Expiry date | Mar 19, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/125
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A graphics system reduces fetching from memory of color-key pixels when video pixels from a video-overlay window are displayed. A frame buffer is divided into multi-line, multi-pixel blocks that are arranged in block-rows and block-columns. Each block-row has primary and secondary row indicator bits and each block-column has two column indicator bits. When the primary row indicator bit is cleared, all pixels in the block-row are fetched from a frame-buffer memory. When the primary row indicator is set, a secondary row indicator bit selects either first or second column indicator bits for reading. When the selected column indicator bit for a block-column is set, fetching of pixels from the frame buffer memory is skipped. Instead, dummy color-key pixels are generated and inserted into the pixel stream. These dummy pixels match the color key and cause video pixels to be sent to the display. Memory fetching is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.