Resilient switch
US7400832B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Jul 15, 2008 |
| Priority date | — |
| Expiry date | Sep 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2011/0043
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A switch for the switching of communications system signals, with m input ports and n output ports, comprising two or more parallel switch matrices, each of size m×n, combined so that each switch matrix contributes to the available output power at each output port. The failure of one of the switch matrices, or one of the transmission paths therein, will therefore result only in a small reduction in the output power at the relevant output port, rather than complete power loss as would be the case for a conventional switch This fault condition can be detected using a power imbalance detection circuit in the switch matrix combiner. Additionally, the fault condition, having been detected by the power imbalance detection circuit, may be temporarily compensated by an automatic level control system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.