Matching memory transactions to cache line boundaries
US7401184B2 · kind B2 · utility
1Cited by
3References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2004 |
| Grant date | Jul 15, 2008 |
| Priority date | — |
| Expiry date | Jun 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In general, in one aspect, the disclosure describes a method that includes generating multiple cache line accesses to multiple respective cache lines of a cache as required to satisfy an access to data specified by a single instruction of a processing element specifying an access to data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.