Sub-picosecond multiphase clock generator
US7403054B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2007 |
| Grant date | Jul 22, 2008 |
| Priority date | — |
| Expiry date | Dec 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit apparatus and method for generating multiphase clocks in a delay lock loop (DLL) at sub-picosecond granularity. The circuit and method of the invention involves locking a number of cycles M in an N stage DLL, e.g., M cycles, where M is an prime number, which results in clock edges in each cycle that are not located at the same phase locations in each of the M cycles. Any of the phase locations from any of the cycles can be used to generate a clock edge for all cycle in the system application. This requires a special technique to “lock” the DLL loop over a M cycle period instead of a one cycle period. The benefit is that it improves the clock placement granularity by a factor of M over the previous art.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.