Non-volatile semiconductor memory device and method for operating a non-volatile memory device
US7403417B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 23, 2005 |
| Grant date | Jul 22, 2008 |
| Priority date | — |
| Expiry date | May 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate to non-volatile memory devices and their methods of manufacture. Embodiments comprise an array of non-volatile memory cells, the array comprising a multiplicity of array columns having at least one redundant column of non-volatile memory cells adapted to replace a defective array column, a column decoder, and a column redundancy unit. The column decoder is adapted to receive an address of a memory cell to which data is to be written or from which data is to be read. The column redundancy unit is adapted to decide whether the decoded address is to be written to or read from an array from or a redundant column. The data required by the column redundancy unit is stored in a column redundancy memory, which is connected to the column redundancy unit by means of a dedicated column redundancy bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.