Galois field multiplier array for use within a finite field arithmetic unit
US7403964B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2003 |
| Grant date | Jul 22, 2008 |
| Priority date | — |
| Expiry date | Nov 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/724
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Galois field multiplier array includes a 1st register, a 2nd register, a 3rd register, and a plurality of multiplier cells. The 1st register stores bits of a 1st operand. The 2nd register stores bits of a 2nd operand. The 3rd register stores bits of a generating polynomial that corresponds to one of a plurality of applications (e.g., FEC, CRC, Reed Solomon, et cetera). The plurality of multiplier cells is arranged in rows and columns. Each of the multiplier cells outputs a sum and a product and each cell includes five inputs. The 1st input receives a preceding cell's multiply output, the 2nd input receives at least one bit of the 2nd operand, the 3rd input receives a preceding cell's sum output, a 4th input receives at least one bit of the generating polynomial, and the 5th input receives a feedback term from a preceding cell in a preceding row. The multiplier cells in the 1st row have the 1st input, 3rd input, and 5th input set to corresponding initialization values in accordance with the 2nd operand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.