Packet data placement in a processor cache
US7404040B2 · kind B2 · utility
5Cited by
4References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2004 |
| Grant date | Jul 22, 2008 |
| Priority date | — |
| Expiry date | Jan 1, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9063
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Packet data received by a network controller is parsed and at least a portion of a received packet is stored by the network controller in both a host memory of a system and also in a cache memory of the central processing unit of the system. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.