Data selection circuit for performance counter
US7404112B2 · kind B2 · utility
1Cited by
11References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2003 |
| Grant date | Jul 22, 2008 |
| Priority date | — |
| Expiry date | Jan 23, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the invention is directed to a data selection circuit for a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The data selection circuit is connected to receive the debug data and comprises logic for receiving the debug data as a plurality of N-bit portions of block-aligned data and outputting a designated one of the N-bit portions; and circuitry for providing to the receiving logic a control signal for designating one of the N-bit portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.