Patent · US Active

Ultra low pin count interface for die testing

US7405586B2 · kind B2 · utility

13Cited by

4References

24Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Sunil Gupta · Austin, US
Reed Linde · Cameron Park, US
Rich Fackenthal · Rancho Cordova, US

Key dates

Filing date	Mar 20, 2006
Grant date	Jul 29, 2008
Priority date	—
Expiry date	Sep 30, 2026

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/5602
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus, a method and a system to test a device. An input/output (I/O) block communicates with an external tester to receive test data and to send test result using first and second communication modes. A logic block parses the test data. A memory stores microcode from the parsed test data. The microcode contains a test program to test a circuit. A controller executes the test program.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.