Variable delay clock circuit and method thereof
US7405604B2 · kind B2 · utility
3Cited by
18References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2006 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | Sep 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for generating an output clock is disclosed. The apparatus comprises: N variable offset clock circuits for receiving N input clocks and for generating N intermediate clocks having N phase offsets controlled by N intermediate signals, respectively, where N>1; a clock multiplexer for selecting one of the N intermediate clocks as the output clock according to a finite-state signal having N possible states; and a finite-state-machine for receiving a control signal and the N intermediate clocks and for generating the finite-state signal and the N intermediate signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.