Power manager with selective load reduction
US7406365B2 · kind B2 · utility
9Cited by
6References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2006 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | Jan 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02J1/14
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a power manager may be coupled to a load circuit and configured to receive an input signal indicating a line disturbance on a power supply line and to reduce a load requirement of the load circuit in accordance with the received signal. The power manager may be configured to selectively reduce power to components with low entrance latency while continuing to provide full power to components with high entrance latency. Other embodiments are disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.