Patent · US Active

Adder structure with midcycle latch for power reduction

US7406495B2 · kind B2 · utility

0Cited by

4References

3Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Wilhelm Haller · Winnenden, DE
Rolf Sautter · Nagold, DE
Christoph Wandel · Holzgerlingen, DE
Ulrich Weiss · Holzgerlingen, DE

Key dates

Filing date	Oct 26, 2004
Grant date	Jul 29, 2008
Priority date	—
Expiry date	Jun 12, 2026

Classification

Technology area (CPC G)Physics
CPC primaryG06F2207/3872
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage with static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.