Distributed FIFO
US7406564B1 · kind B1 · utility
2Cited by
8References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 23, 2005 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | May 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or more local memory arrays into a single, larger functional unit. One exemplary embodiment of the present invention provides a FIFO made up of a number of FIFO sub-blocks connected in series. Each FIFO sub-block includes local read and write address counters such that read and write addresses are not bused between the FIFO sub-blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.