Ring interconnect with multiple coherence networks
US7406566B2 · kind B2 · utility
13Cited by
3References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 3, 2005 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | Apr 20, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies, while reducing power within an integrated circuit. More particularly, embodiments of the invention include a plurality of cache agents that each communication with the same protocol agent, which may or may not be integrated within any one of the cache agents. Embodiments of the invention also include protocol agents capable of storing multiple sets of data from different sets of cache agents within the same clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.